Anti-Tamper Digital Clocks Can Be Fun For Anyone

Anti-Tamper Digital Clocks Can Be Fun For Anyone

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utilizing the clock to induce an Examine circuit that works by using the plurality of delayed monotone alerts to detect a clock fault.

32. The apparatus for detecting voltage tampering as outlined in claim 30, wherein the means for triggering the means for assessing works by using a clock edge at an conclude in the evaluate time period to set off the indicates for analyzing.

suggests for delaying the monotone signal to create a plurality of delayed monotone indicators obtaining discretely raising hold off occasions involving a least delay time and also a most hold off time and every on the plurality of delayed monotone alerts getting either a a single or simply a zero logic value;

an Consider circuit, activated with the clock, that employs the main plurality of delayed monotone signals or the 2nd plurality of delayed monotone alerts to detect a clock fault.

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With further more reference to FIG. 7, An additional element of the invention may perhaps reside within an equipment for detecting clock tampering, comprising: a primary circuit 750A, a primary plurality of resettable delay line segments 710, a second circuit 750B, a second plurality of resettable hold off line segments 720, and an Assess circuit 240. The 1st circuit provides a primary monotone sign through a primary clock Consider time period related to a clock. The primary plurality of resettable hold off line segments Every hold off the 1st monotone signal to produce a respective first plurality of delayed monotone indicators. Resettable hold off line segments amongst a resettable hold off line segment linked to a minimal hold off time as well as a resettable hold off line section associated with a highest hold off time are Each and every connected to discretely increasing delay instances. The 2nd circuit presents a 2nd monotone signal all through a second clock Examine time frame connected to the clock.

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The next clock evaluate period of time covers a distinct time than the primary clock Consider time period, as can be enforced by an inverter 730. The 2nd plurality of resettable delay line segments Each individual delay the 2nd monotone sign to deliver a respective 2nd plurality of delayed monotone signals. Resettable hold off line segments concerning a resettable delay line phase associated with a minimal hold off time along with a resettable hold off line segment related to a utmost hold off time are Just about every associated with discretely escalating delay periods. The Consider circuit is induced via the clock (e.g., EVAL) and works by using the 1st plurality of delayed monotone signals or the second plurality of delayed monotone indicators to detect a clock fault. A multiplexer 760 may pick which of the primary or second plurality of delayed monotone signals are active to be presented to the Examine circuit.

38. The apparatus for detecting voltage tampering as described in assert 37, whereby the resettable delay line segments are reset throughout a reset time period, whereby the reset time frame is just before the Examine period of time.

24. The method for detecting voltage tampering as defined in assert 23, even further comprising: resetting the resettable hold off line segments during a reset time frame, whereby the reset time frame is before the evaluate time frame.

In more specific aspects of the invention, the method may more contain resetting the resettable delay line segments during a reset period of time.

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